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<tr><th> Error 01: <br></th></tr>
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	This error is generated if the same signal is being assigned<br>
	in multiple always blocks and/or assign statements.<br>
	The error lists what line they are on.<br>
	The List will also contain ports of vectors that are falling under<br>
	this rule.<br><br>
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<tr><th> Example: <br></th></tr>
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module MultiplyDrivenSignals(<br>
  input wire one,<br>
  output reg two,<br>
  output wire three<br>
  );<br>
  <br>
	wire four;<br>
<br>  
	reg five;<br>
<br>
  <br>
  <br>
	always@(one)begin<br>
		two = 0;<font color=#00ff00>//error report assigned in second always</font><br>  
	end<br>
  <br>
  <br>
	always@(two)begin<br>
    <br>
		five = 0;<br>
    <br>
		two = 1;<font color=#00ff00>//error report assigned in first always</font><br>
  <br>
	end<br>
<br>
  <br>
  <br>
	assign three = 0; <font color=#00ff00>//error report assigned in assign statement below</font><br>
  <br>
	assign three = 1; <font color=#00ff00>//error report assigned in error statement above</font>  <br>
	assign four = 0;<br>
  <br>
<br>
endmodule<br>
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<th>Probable Solution<br></th>
<br>
<td>
To Fix make sure there is only one assign statement per variable and that the<br>
variable is not being set in multiple always blocks<br>
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